Field
The disclosed technology generally relates to semiconductor devices, and more particularly to field effect semiconductor devices and methods of making the same.
Description of the Related Technology
The semiconductor industry continues to make unrelenting efforts to further increase the device density, or the number of devices, e.g., transistors, per unit area in integrated circuits. Recently, some device structures, e.g., transistor structures having vertical channel structures, have been proposed to further increase the device density. For instance, isolated vertical nanowires, e.g., self-aligned vertical nanowires, have been used to form transistors. Such nanowires, however, may limit the cross-sectional area of the channel of the resulting transistor. Such a reduction in the cross-sectional area of the channel can limit the performance of such devices, since some device performance parameters, e.g., the drive current or the on-current, can be directly proportional to the cross-sectional area of the channel. Furthermore, using isolated vertical nanowires may consume an undesirable amount of wafer space, leading to lower device density for a given footprint of the integrated circuit.
Very recently, attempts have been made to form fin-based vertical transistors (vertical FinFETs). An example of such a vertical Fin-FET device is disclosed in US 2009/0200604, in which a vertical Fin-FET device fabricated on a silicon-on-insulator (SOI) substrate. The fin structures are defined in the silicon layer present on the oxide insulator by etching parallel trenches in the silicon. Heavily doped silicon, e.g., N+ doped silicon is then deposited on bottom regions of the trenches and subsequently heated to diffuse the doping elements from the silicon present in the trenches into the base portion of the fin structure. Doping of the top portion of the fin is performed by ion implantation. This method has several disadvantages. First, it often requires a SOI substrate, which is a particularly expensive substrate. Second, the doping methods used for both the base and the top of the fin can introduce in homogeneities in the doping profile and/or diffuse boundaries between the doped regions (e.g., top and base portions) and the undoped region (e.g., middle channel portion) of the fin, leading to performances that are not optimal and variability from one device to another. Third, this way to dope the base of the fin often requires several processes in addition to the formation of the fin itself, such as the deposition of the doped material in the trenches, and the thermal treatment.
Thus, there is a need for new vertical fin-based transistors and methods for producing the same, to address one or more of the problems identified above.